page 1 of 8 document no. 70-0144-01 www.psemi.com ?2005 peregrine semiconductor corp. all rights reserved. figure 2. package type rfc rf1 rf2 c1 75 75 75 c2 cmos control driver 20-lead 4x4 mm qfn the PE4256 is an ultracmos? switch designed for catv applications, covering a broad frequency range from dc up to 3000 mhz. this single-supply spdt switch integrates a two- pin cmos control interface. it also provides low insertion loss with extremely low bias requirements while operating on a single 3-volt supply. in a typical catv application, the PE4256 provides for a cost effective and manufacturable solution when compared to mechanical relays. the PE4256 is manufactured in peregrine?s patented ultra thin silicon (utsi ? ) cmos process, offering the performance of gaas with the economy and integration of conventional cmos. product specification 75 ? spdt catv ultracmos? switch dc - 3.0 ghz product description figure 1. functional diagram PE4256 features ? 75 ? characteristic impedance ? integrated 75 ? 0.25 watt terminations ? ctb performance of -90 dbc ? high isolation 65 db at 1000 mhz ? low insertion loss: typically 0.5 db at 5 mhz, 0.9 db at 1000 mhz ? high input ip3: >50 dbm ? cmos two-pin control ? single +3 volt supply operation ? low current consumption: 8 a ? unique all off terminated mode ? 4x4 mm qfn package table 1. electrical specifications @ +25 c, v dd = +3 v (z s = z l = 75 ? ) parameter condition minimum typical maximum units operating frequency 1 dc 3000 mhz insertion loss 5 mhz ? 250 mhz 250 mhz ? 750 mhz 750 mhz ? 1000 mhz 1000 mhz ? 2200 mhz 0.5 0.8 0.9 1.1 0.6 0.95 1.1 1.3 db isolation 5 mhz ? 250 mhz 250 mhz ? 750 mhz 750 mhz ? 1000 mhz 1000 mhz ? 2200 mhz 75 65 62 49 80 70 65 52 db input ip2 2 5 mhz - 1000 mhz 80 dbm input ip3 2 5 mhz - 1000 mhz 50 55 dbm input 1db compression 2 1000 mhz 29 31 dbm ctb / cso 77 & 110 channels; power out = 44 dbmv -90 dbc switching time 50% ctrl to 10/90% rf 2 s video feedthrough 3 5 mhz - 1000 mhz 15 mv pp notes: 1. device linearity will begin to degrade below 1 mhz. 2. measured in a 50 ? system. 3. measured with a 1 ns risetime, 0/3 v pulse and 500 mhz bandwidth
product specification PE4256 page 2 of 8 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0144-01 ultracmos? rfic solutions table 2. pin descriptions table 3. absolute maximum ratings electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. table 4. dc electrical specifications @ 25 c figure 3. pin configuration (top view) no. name description 1 gnd ground 2 gnd ground 3 1 rf1 rf i/o 4 gnd ground 5 gnd ground 6 gnd ground 7 gnd ground 8 1 rfc common 9 gnd ground 10 gnd ground 11 gnd ground 12 gnd ground 13 1 rf2 rf i/o 14 gnd ground 15 gnd ground 16 2 c2 control 2 17 2 c1 control 1 18 3 vss / gnd negative supply option 19 gnd ground 20 vdd supply pad gnd ground pad notes: 1. rf pins 3, 8, and 13 must be at 0 vdc. the rf pins do not require dc blocking capacitors for proper operation if the 0 vdc requirement is met. 2. pins 16 and 17 are the cmos controls that set the three operating states. 3. connect pin 18 to gnd to enable the on-chip negative voltage generator. connect pin 18 to v ss (-3v) to bypass and disable internal -3v supply generator. switching frequency the PE4256 has a maximum 25 khz switching rate when the internal negative voltage generator is used (pin 18=gnd). symbol parameter/condition min max unit v dd power supply voltage -0.3 4.0 v v i voltage on ctrl input -0.3 v dd + 0.3 v p rf rf cw power 24 dbm t st storage temperature -65 150 c t op operating temperature -40 85 c v esd esd voltage (human body model) 1000 v parameter min typ max unit v dd power supply 2.7 3.0 3.3 v i dd power supply current (v dd = 3v, v cntl = 3v) 8 20 a control voltage high 70% v dd v control voltage low 30% v dd v gnd 15 14 13 12 11 3 4 5 2 1 17 16 18 19 20 9 10 8 7 6 ctrl2 gnd gnd gnd gnd gnd rfc vdd ctrl1 vss/gnd gnd gnd gnd rf2 gnd, rf2 term. gnd gnd, rf1 term. rf1 gnd gnd 75 ? 75 ? 150 ? 150 ?
product specification PE4256 page 3 of 8 document no. 70-0144-01 www.psemi.com ?2005 peregrine semiconductor corp. all rights reserved. table 5. rf path truth table table 6. termination truth table notes: 1. the operation of the PE4256 is not supported or characterized in the c1=v dd and c2=v dd state. 2. ?x? denotes termination enabled. c1 c2 rfc ? rf1 rfc ? rf2 low low off off low high off on high low on off high high n/a 1 n/a 1 c1 c2 rfc ? 75 ? rf1 ? 75 ? rf2 ? 75 ? low low x 2 x 2 x 2 low high x 2 high low x 2 high high n/a 1 n/a 1 n/a 1
product specification PE4256 page 4 of 8 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0144-01 ultracmos? rfic solutions evaluation kit the spdt switch evaluation kit was designed to ease customer evaluation of the PE4256 spdt switch. the rf common port (rfc) is connected through a 75 ? transmission line to j2. port 1 and port 2 are connected through 75 ? transmission lines to j1 and j3. a through transmission line connects f connectors j4 and j5. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the board is constructed with four metal layers in fr4 material with a total thickness of 0.062?. the transmission lines were designed using a coplanar waveguide with ground plane (28 mil core, 21 mil width, 30 mil gap). j6 provides a means for controlling dc and digital inputs to the device. the provided jumpers short the package pin to ground for logic low. when the jumper is removed, the pin is pulled up to v dd for logic high. when the jumper is in place, 3 a of current will flow through the 1 m ? pull-up resistor. this extra current should not be attributed to the device. proper pcb design is essential for full isolation performance. this evaluation board demonstrates good trace and ground management for minimum coupling and radiation. figure 4. evaluation board layouts figure 5. evaluation board schematic peregrine specification 102/0195~02a peregrine specification 101/0148~03a
product specification PE4256 page 5 of 8 document no. 70-0144-01 www.psemi.com ?2005 peregrine semiconductor corp. all rights reserved. -100 -90 -80 -70 -60 -50 -40 0 500 1000 1500 2000 2500 3000 rf1 - rf2 (rf1 thru) rf1 - rf2 (rf2 thru) rf1 - rf2 (rf1 & 2 open) isolation (db) frequency (mhz) -100 -90 -80 -70 -60 -50 -40 0 500 1000 1500 2000 2500 3000 rfc - rf1 (rf2 open) rfc - rf2 (rf1 open) isolation (db) frequency (mhz) -100 -90 -80 -70 -60 -50 -40 0 500 1000 1500 2000 2500 3000 rfc - rf1 (rf2 closed) rfc - rf2 (rf1 closed) isolation (db) frequency (mhz) -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 500 1000 1500 2000 2500 3000 25c -40c 85c insertion loss (db) frequency (mhz) typical performance data from -40c to +85c, 75 ? impedance figure 7. input to output isolation figure 9. isolation ? rf1 to rf2 figure 8. input to output isolation figure 6. insertion loss (rfc to rf1 or rf2)
product specification PE4256 page 6 of 8 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0144-01 ultracmos? rfic solutions 0 10 20 30 40 50 60 0 500 1000 1500 2000 2500 3000 input ip3 1db compression power (dbm) frequency (mhz) -35 -30 -25 -20 -15 -10 -5 0 0 500 1000 1500 2000 2500 3000 rfc - rf2 closed rf2 terminated return loss (db) frequency (mhz) -35 -30 -25 -20 -15 -10 -5 0 0 500 1000 1500 2000 2500 3000 rfc - rf1 closed rf1 terminated return loss (db) frequency (mhz) -35 -30 -25 -20 -15 -10 -5 0 0 500 1000 1500 2000 2500 3000 rfc terminated rfc - rf1 closed return loss (db) frequency (mhz) typical performance data @ +25c, 75 ? impedance (unless otherwise noted) figure 11. rf1 return loss figure 13. linearity figure 12. rf2 return loss figure 10. rfc return loss (50 ? system impedance)
product specification PE4256 page 7 of 8 document no. 70-0144-01 www.psemi.com ?2005 peregrine semiconductor corp. all rights reserved. 1.00 1.00 2.00 2.00 0.23 0.10 c a b exposed pad 4.00 detail a 16 15 11 5 1 6 20 10 0.50 typ 2.00 typ 0.55 2 1 detail a 0.18 0.18 0.435 0.435 seating plane 0.08 c 0.10 c 0.020 0.20 ref exposed pad & terminal pads 0.80 - c - 2.00 x 2.00 2.00 2.00 4.00 4.00 - b - - a - index area 0.25 c 2. coplanarity applies to the exposed heat sink slug as well 1. dimension applies to metallized terminal and is measured as the terminals. between 0.25 and 0.30 from terminal tip. 20-lead 4x4 mm qfn figure 14. package drawing (mm) figure 15. tape and reel drawing table 7. ordering information order code part marking description package shipping method 4256-01 4256 PE4256-20qfn 4x4 mm-75a 20-lead 4x4 mm qfn 75 units / tube 4256-02 4256 PE4256-20qfn 4x4 mm-3000c 20-lead 4x4 mm qfn 3000 units / t&r 4256-00 PE4256-ek PE4256-20qfn 4x4 mm-ek evaluation kit 1 / box 4256-51 4256 PE4256g-20qfn 4x4 mm-75a green 20-lead 4x4 mm qfn 75 units / tube 4256-52 4256 PE4256g-20qfn 4x4 mm-3000c green 20-lead 4x4 mm qfn 3000 units / t&r
product specification PE4256 page 8 of 8 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0144-01 ultracmos? rfic solutions sales offices united states peregrine semiconductor corp. 9450 carroll park drive san diego, ca 92121 tel 1-858-731-9400 fax 1-858-731-9499 japan peregrine semiconductor k.k. 5a-5, 5f imperial tower 1-1-1 uchisaiwaicho, chiyoda-ku tokyo 100-0011 japan tel: 011-81-3-3502-5211 fax: 011-81-3-3502-5213 europe for a list of representatives in your area, please refer to our web site at: www.psemi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the data sheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a dcn (document change notice). peregrine semiconductor europe batiment maine 13-15 rue des quatre vents f- 92380 garches, france tel: 011- 33-1-47-41-91-73 fax : 011-33-1-47-41-91-73 china peregrine semiconductor 28g, times square, no. 500 zhangyang road, shanghai, 200122, p.r. china tel: 011-86-21-5836-8276 fax: 011-86-21-5836-7652 the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos is a trademark of peregrine semiconductor corp.
|
